2. Assignment 2

  • Worth: 5%

  • DUE: Monday March 3, 11:55pm; submitted on MOODLE.

2.1. Provided Files

Incomplete Digital files are provided for the questions. These files contain tests, a resizable designated space for building circuits, and labelled inputs, outputs, and other components.

These files can be downloaded from here.

Uncompress this folder and open the files within Digital. Each question specifies which of the file to work in.

2.2. Part 1 — Selectors

  1. Create a circuit where the output of some input can be inverted with some other signal

    • Use the provided file titled “1-bit_inverter.dig”

    • Below is a truth table describing the desired functionality

    Bit Inverter Truth Table

    Input

    Invert

    Output

    0

    0

    0

    0

    1

    1

    1

    0

    1

    1

    1

    0

  2. Create a 1 bit selector circuit such that one of two inputs is mapped to the output with the following constraints

    • A multiplexer may not be used

    • Only drivers and not gates may be used

    • Use the provided file titled “2-input_selector.dig”

    • Below is a truth table describing the desired functionality

      • Here, A and B are variable inputs that can take on either 0/1

    1 Bit Selector Truth Table

    \(i_{0}\)

    \(i_{1}\)

    \(s\)

    \(o\)

    A

    B

    0

    A

    A

    B

    1

    B

  3. Create a circuit that can map one of two inputs to one of two outputs with the following constraints

    • A multiplexer may not be used

    • Only drivers and not gates may be used

    • Hint: Use the general bit selector design from the previous question

    • Use the provided file titled “3-input_output_selector.dig”

    • Below is a truth table describing the desired functionality

      • Note that Z denotes the high impedance state and does not represent some variable input

    1 Bit Input/Output Selector Truth Table

    \(i_{0}\)

    \(i_{1}\)

    \(s_{i}\)

    \(s_{o}\)

    \(o_{0}\)

    \(o_{1}\)

    A

    B

    0

    0

    A

    Z

    A

    B

    0

    1

    Z

    A

    A

    B

    1

    0

    B

    Z

    A

    B

    1

    1

    Z

    B

  4. Create a circuit that can map one of four inputs to one of four outputs with the following constraints

    • Multiplexers and demultiplexer may be used

    • Use the provided file titled “4-plex_input_output_selector.dig”

2.3. Part 2 — JK Flip-Flops

An SR flip-flop is similar to an SR latch except that the flip-flop only changes state on a clock pulse, similar to that of a D flip-flop.

A JK Flip Flop is similar to an SR flip-flop, except that when both inputs (called \(J\) and \(K\), for \(S\) and \(R\) respectively) are 1, the outputs \(Q\) and \(\lnot Q\) toggle/oscillate.

JK Flip-Flop Truth Table

\(C\)

\(J\)

\(K\)

\(Q\)

\(\lnot Q\)

\(Q\)

\(\lnot Q\)

C

0

0

0

1

0

1

C

0

0

1

0

1

0

C

0

1

0

1

0

1

C

0

1

1

0

0

1

C

1

0

0

1

1

0

C

1

0

1

0

1

0

C

1

1

0

1

1

0

C

1

1

1

0

0

1

This toggle feature has an interesting property that the \(Q\) output toggles at half the frequency of the clock input. In other words, it takes two clock cycles for \(Q\) to cycle once.

  1. Create a JK flip-flop

    • Use the provided file titled “5-JK_flipflop.dig”

    • Feel free to research designs of a JK flop-flop

      • WARNING: Most designs available will fail due to race conditions

    • HINT: Use the idea of the D flip-flop design for the JK flop-flop to resolve the race condition problem

      • WARNING: Unlike the the D flip-flop, have the final \(Q\) value latch when the clock goes low

  2. Create a 4 bit counting circuit that increments 1 every clock pulse with 4 JK flip-flops

    • For example, each arrow corresponds to one clock pulse

      • 0000 -> 0001 -> 0010 -> 0011 -> 0100 -> 0101 -> … -> 1111 -> 0000 -> …

    • Use the provided file titled “6-counter.dig”

    • Use the JK flip-flop design from the above question and not the built in component

      • Using Digital’s built in JK flip-flop will not produce the desired result

    • HINT: Chain JK flip-flops together

    • HINT: Set each JK flip-flop’s \(J\) and \(K\) inputs to 1 with a constant

      • This puts the JK flip-flops into their toggle/oscillate state

    • Ignore the \(\lnot Q\)s for this circuit

    • Note that one should expect the outputs to start on some arbitrary value when running the circuit

      • Do not expect the outputs to start at 0000

2.4. Part 3 — RAM

  1. Create a 4 byte RAM design with four 8 bit register components, a multiplexer, demultiplexer, and a driver

    • Use the provided file titled “7-4_byte_ram.dig”

    • This file already contains the components needed in the workspace

      • The design must use these components

      • No other components may be added to the design

2.5. Some Hints

  • Work on one part at a time

  • Some parts of the assignment build on the previous, so get each part working before you go on to the next one

  • Test each design as you build it

    • This is a really nice thing about these circuits; you can run your design and see what happens

    • Mentally test before you even implement — what does this design do? What problem is it solving?

  • If you need help, ask

    • Drop by office hours

2.6. Some Marking Details

Warning

Just because your design produces the correct output and the tests pass, that does not necessarily mean that you will get perfect, or even that your design is correct.

Below is a list of both quantitative and qualitative things we will look for:

  • Correctness?

  • Did you follow instructions?

  • Label names?

  • Design, layout, and style?

  • Did you do weird things that make no sense?

2.7. What to Submit to Moodle

  • Submit your completed Digital (.dig) files to Moodle

  • Do not compress the files before uploading to Moodle

Warning

Verify that your submission to Moodle worked. If you submit incorrectly, you will get a 0.

2.8. Assignment FAQ