9. Enhancing Designs

  • Feel free to use your laptop

  • You are strongly encourage to work with others

    • When you get stuck, ask those sitting around you for help

    • Get used to working together in the labs

    • Peer teaching and peer learning has been empirically shown to be very effective

9.1. Including Hardware

For this part of the lab, use the ESAP digital file from here.

  1. Include the hardware for AND, OR, and NOT operations to the ESAP system

    • These operators will work similar to addition to subtraction in the existing design

      • Apply the operator to the contents of the A and B registers, and store the result in the A register

      • NOT only works on the contents of the A register

  2. These new operators require control signals

    • Connect these new control signals to the control logic loop up table

9.2. Control Logic

For this part of the lab, use the script for generating the control logic patterns from here.

  1. Although the new control logic is connected, ensure the look up table has the correct number of outputs

    • Ensure the number of outputs from the look up table includes the new control signals

  2. Update the contents of the look up table to allow for three new machine code instructions

    • An instruction for each of the operators allowed by the new hardware

    • Use the 3 unused patterns for these instructions

    • Use the Python script to create a new hex file for the look up table

  3. Write machine code programs to ensure each of these new instructions work properly

9.3. Enhancing the Previous Lab

  1. If not already completed, finish the design from the previous lab

9.3.1. 16 Bit Bus

  1. In a separate circuit, create a design for a 16 bit bus using

    • RAM with an 8 bit address space and 8 bit addressability (\(265 \times 8\) bits)

    • A counter

    • Two 8 bit instruction registers

      • Even counter values retrieve data from even RAM addresses, and odd values retrieve from odd memory addresses

      • Fetching from RAM takes 2 clock cycles

      • One of the two 8 bit registers will always store bit patterns from the even or odd memory addresses

      • The output from these two 8 bit registers make up the 16 bit bus

  2. Add this 16 bit bus to the design from the previous labs

    • Include it in the design such that bit patterns can be written to RAM and executed automatically

      • The bit patterns as discussed in previous labs

    • Not all of the 16 bits will be needed when interfacing with the previous design

    • The program counter enable will likely need to be controlled carefully